Proposed on-chip test structure to quantify trap densities within flash memories

  • Authors:

  • V. Verma;A. Swaneck

  • Affiliations:

  • -;-

  • Venue:
  • MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
  • Year:
  • 1996

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Abstract

Abstract: Degradation of the program/erase characteristics of Flash memory due to cycling is an industry wide reliability concern. This degradation in performance is associated with trapped charges present within the memory cells dielectric. The implementation of an on chip test structure is proposed, allowing trapping characteristics of the Flash memory cells to be monitored. This paper discusses the on-chip test structure, program/erase characteristics of Flash memories, and electron trap density measurements.