A Compiler Algorithm to Reduce Invalidation Latency in Virtual Shared Memory Systems

Authors:
M. F. P. O'Boyle;A. P. Nisbet;R. W. Ford
Affiliations:
-;-;-
Venue:
PACT '96 Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques
Year:
1996

Citing 0
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Towards general and exact distributed invalidation

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Abstract

This paper presents a new compiler algorithm to eliminate invalidation traffic in virtual shared memory using a hybrid distributed invalidation scheme. It aggressively exploits static scheduling and data layout to accurately determine only those instances when invalidation is necessary, thus avoiding the additional read misses of previous schemes. Equations determining precisely what data should be invalidated are presented and followed by the derivation of approximations amenable to compiler manipulation. Compiler-directed invalidation in the presence of arbitrary control-flow is described and the definition of a compiler algorithm is presented. Preliminary experimental results on three programs show that this analysis can drastically reduce the amount of invalidation traffic and write misses.