Dependability Analysis of a Fault-Tolerant Processor

  • Authors:
  • Cristian Constantinescu

  • Affiliations:
  • -

  • Venue:
  • PRDC '01 Proceedings of the 2001 Pacific Rim International Symposium on Dependable Computing
  • Year:
  • 2001

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Abstract

Advances in semiconductor technology have improvedthe performance of integrated circuits, in general, andmicroprocessors, in particular, at a dazzling pace.Although, smaller transistor dimensions, lower powervoltages and higher operating frequencies havesignificantly increased the circuit sensitivity to transientand intermittent faults.In this paper we present thearchitecture of a fault-tolerant processor and analyze itsdependability with the aid of a generalized stochasticPetri net (GSPN) model.he effect of transient andintermittent faults is evaluated.It is concluded that fault-tolerance mechanisms, usually employed by custom designed systems, have to be integrated into commercial-off-the-shelf (COTS) devices, in order to mitigate the impact of higher rates of occurrence of the transient and intermittent faults.