SET Emulation Under a Quantized Delay Model
Journal of Electronic Testing: Theory and Applications
PPAM'05 Proceedings of the 6th international conference on Parallel Processing and Applied Mathematics
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When designing a VL I circuits, most of the efforts are now performed at levels of abstractions higher than gate. Correspondingly to this clear trend, there is a growing request to tackle safety-critical issues directly at the RT-level. This paper presents a complete environment for considering safety issues at the RT level. The environment was implemented and tested by an industry for devising a sample safety-critical device. Designers were permitted to assess the effects of transient faults, automatically add fault-tolerant structures, and validate the results working on the same circuit descriptions and acting in a coherent framework. The evaluation showed the effectiveness of the proposed environment.