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The benefits of hardware support for shared memory versus those formessage passing are difficult to evaluate without an in-depth study ofreal applications on a common platform. We evaluate the communicationmechanisms of the MIT Alewife machine, a multiprocessor which providesintegrated cache-coherent shared memory, message passing, and DMA. Weperform this evaluation with ``best-effort'''' implementations whichsolve several sparse, irregular benchmark problems with apreconditioned conjugate gradient sparse matrix solver (ICCG). We find that machines with fast global memory operations do not needmessage passing or bulk transfer to support our irregular problems.This is primarily due to three reasons. First, a 5-to-1 ratio betweenglobal and local cache misses makes memory copies in bulkcommunication expensive relative to communication via shared memory.Second, although message passing has synchronization semanticssuperior to shared memory for data-driven computation, efficientshared memory can overcome this handicap by using globalread-modify-writes to change from the traditional owner-computes modelto a producer-computes model. Third, bulk transfers can resultin high processor idle times in irregular applications.