ACM Transactions on Computer Systems (TOCS)
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Modern microprocessor architectures are very complex designs. Consequently, they exhibit many idiosyncrasies. In fact, situations exist in which the addition or removal of a single instruction changes the performance of a program by a factor of 3 to 4. I call such situations performance anomalies. Avoiding these situations requires detailed understanding of the underlying architecture. Unfortunately, due to market competition, microprocessor vendors are unwilling to release the detailed implementation information necessary to understand an architecture until long after the microprocessors have been on the market. Through a case study of the SUN UltraSPARC, I show how these anomalies can be concealed, although only limited information is provided by the vendor. I explain the cause of four performance anomalies observed on the UltraSPARC, and present an algorithm to conceal each of them. I implemented these algorithms in an assembly code restructuring tool which yields speedups of 2.2% on average for the SPECint benchmark suite, and up to 8.9% on individual benchmarks.