LOGIC SIMULATION ON A MULTIPROCESSOR

  • Authors:

  • E. Bradley

  • Affiliations:

  • -

  • Venue:
  • LOGIC SIMULATION ON A MULTIPROCESSOR
  • Year:
  • 1986

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Abstract

The performance of circuit simulators running on SISD computers is fundamentally limited by the Von Neumann bottleneck. Multiprocessors do not share this limitation. The task of solving the equations for the many parallel signal paths found in most circuits lends itself readily to concurrent computation. For both of these reasons, parallel processing is a highly promising approach to circuit simulation. This thesis explores several facets of this problem. The logic simulator CONSIM was implemented in the parallel language Multilisp, which contains special constructs for dispatching tasks in parallel. A model for the simulator''s behavior was developed using a series of experiments. The analysis explains the effects upon CONSIM''s performance of several parameters, including: the number of nodes in the multiprocessor, circuit size and topology, and the algorithms for generating the simulation code and for taking advantage of its inherent parallelism. The final generation of these algorithms exposed and exploited significant parallelism, but did not attain linear speedup.