Structure handling in data-flow systems
IEEE Transactions on Computers - The MIT Press scientific computation series
I-structures: data structures for parallel computing
ACM Transactions on Programming Languages and Systems (TOPLAS)
A Hybrid Scheme for Processing Data Structures in a Dataflow Environment
IEEE Transactions on Parallel and Distributed Systems
ALICE a multi-processor reduction machine for the parallel evaluation CF applicative languages
FPCA '81 Proceedings of the 1981 conference on Functional programming languages and computer architecture
Copying operands versus copying results: A solution to the problem of large operands in FFP'S
FPCA '81 Proceedings of the 1981 conference on Functional programming languages and computer architecture
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A data flow computer is one which achieves enormous concurrency of instruction execution through a machine architecture that acts directly on a data dependency graph of the program. To handle arrays and data structures effectively, a data flow computer must have access to a memory system which can handle large numbers of concurrent transactions. This thesis presents a design for such a memory. A "cache" mechanism is presented for improving the performance of the system, and a mechanism is given for using sequential-access devices such as shift registers as the memory medium. The memory system design uses the "packet communication" concept, in which the components of the system communicate only through the transmission of fixed size "packets" of data.