Slicing Hierarchical Automata for Model Checking UML Statecharts
ICFEM '02 Proceedings of the 4th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
A discrete-time UML semantics for concurrency and communication in safety-critical applications
Science of Computer Programming - Formal methods for components and objects pragmatic aspects and applications
AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
UML Automatic Verification Tool with Formal Methods
Electronic Notes in Theoretical Computer Science (ENTCS)
Formalising UML state machines for model checking
UML'99 Proceedings of the 2nd international conference on The unified modeling language: beyond the standard
Design verification for product line development
SPLC'05 Proceedings of the 9th international conference on Software Product Lines
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The Unified Modelling Language (UML) is a standardised notation for describing object-oriented software designs. We present vUML, a tool that automatically verifies UML models. vUML verifies models where the behaviour of the objects is described using UML Statecharts diagrams. It supports concurrent and distributed models containing active objects and synchronous and asynchronous communication between objects. The tool uses the SPIN model checker to perform the verification, but the user does not have to know how to use SPIN or the PROMELA language. If an error is found during the verification, the tool creates a UML sequence diagram showing how to reproduce the error in the UML model.