From UML sequence diagrams and statecharts to analysable petri net models
WOSP '02 Proceedings of the 3rd international workshop on Software and performance
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The Unified Modelling Language (UML) is becoming the de-facto standard for object-oriented software modelling, including software for embedded systems. In this paper, we show how to model the Production Cell, a standard example for evaluating embedded systems design notations, using UML. Then, we use the vUML tool to verify our model of the Production Cell. vUML is a tool developed by the authors to verify UML models. Although, vUML internally uses the SPIN model-checker, the input model and the results from the verification are expressed using the UML notation, thus hiding the model-checking formalism from the user. vUML checks that a model is free of deadlocks, livelocks and that all the invariants are always preserved. vUML can not verify real-time properties but we explain how to use vUML to identify the real-time constrains of a model. We also show how to use the object-oriented decomposition of the problem that is given by an UML class diagram, to reduce the complexity of the model-checking problem. We conclude that the vUML tool helps the designer to verify the software of distributed object-oriented embedded systems, without learning how to use a model-checker.