TLB For Free: In-Cache Address Translation For A Multiprocessor

  • Authors:
  • Scott A Ritchie

  • Affiliations:
  • -

  • Venue:
  • TLB For Free: In-Cache Address Translation For A Multiprocessor
  • Year:
  • 1985

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Abstract

In the design of SPUR, a high-performance multiprocessor workstation, the need for large "snooping" caches suggests a new approach to virtual address translation. By performing this translation in each processor''s virtual cache, the need for separate translation lookaside buffers is eliminated. Trace-driven simulations show that normal cache behavior is only minimally effected, and that unless an extremely large and complex TLB were built, using a separate device would actually reduce system performance.