Program optimization for instruction caches
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IEEE Transactions on Computers
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GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
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ACM Transactions on Embedded Computing Systems (TECS)
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Program performance can be improved on machines with virtual memory by reorganizing the program''s address space. We address the question whether reorganization could benefit programs on machines with instruction caches. We have performed experiments to determine the efficacy of restructuring using simple reordering algorithms and profile data, concluding that performance improvement can be obtained relatively cheaply. Experiments show improvements in rise rates on the order 30% to 50%, and sometimes as high as 50% to 80%, by performing a simple algorithm that relocates only 3% to 5% of the basic blocks of a program.