The physical mapping problem for parallel architectures
Journal of the ACM (JACM)
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THE `DIOGENES'' METHODOLOGY PRODUCES DESIGNS FOR FAULT-TOLERANT VLSI PROCESSOR ARRAYS IN THREE STAGES. IN THE FIRST STAGE, THE DESIRED ARRAY IS VIEWED AS AN UNDIRECTED GRAPH AND IS `EMBEDDED IN A BOOK''; THIS STAGE HAS BEEN WELL STUDIED. IN THE SECOND STAGE, A (RE)CONFIGURABLE ARRAY OF IDENT- ICAL PHYSICAL PROCESSORS THAT WILL REALIZE THE DESIRED ARRAY IS CONSTRUCT- ED. IN THE THIRD STAGE, THE BOOK-EMBEDDING IS CONVERTED TO AN EFFICIENT FAULT-TOLERANT LAYOUT OF THE ARRAY, BY ASSOCIATING EACH LOGICAL PROCESSOR OF THE BOOK-EMBEDDING WITH A PROCESSOR OF THE PHYSICAL ARRAY, THIS STAGE IS THE FOCUS OF THE CURRENT STUDY. WE CONSIDER TWO QUALITY METRICS FOR LAYOUT, THE FIRST EMBODYING AN IDEALIZED NOTION OF `AVERAGE DELAY'', THAT RELATES TO POWER CONSUMPTION, AND THE SECOND BEING THE `LENGTH OF THE LONGEST RUN OF WIRE''. FOR THE AVERAGE-DELAY MEASURE, WE PRESENT FOUR ALGORITHMS THAT OPTIM ALLY ASSIGN THE `M'' VERTICES OF THE EMBEDDED GRAPH TO THE `N'' FAULT-FREE PROCESSORS THAT HAVE BEEN FABRICATED. THE MOST GENERAL ALGORITHM MAKES NO ASSUMPTIONS ABOUT THE STRUCTURE OF THE ARRAY OR THE PHYSICAL FORMAT OF THE PROCESSORS; IT RUNS IN TIME O(M . (N - M)SUPERSCRIPT 2). THE OTHER ALGOR- ITHMS ASSUME THAT THE PROCESSORS ARE LAID OUT IN SUCH A WAY THAT INTER- PROCESSOR DISTANCES OBEY THE TRIANGLE EQUALITY; THEY RUN IN TIMES RANGING FROM TIME O(MAX{M,N - M} . LOG MIN{M,N - M}) FOR CERTAIN ARRAY STRUCTURES, INCLUDE PYRAMID-ARRAYS, TO TIME O(MAX{M,N - M}) FOR A NARROW CLASS OF ARRAY