Working set prefetching for cache memories

Authors:
Eric E. Johnson
Affiliations:
Parallel Architecture Research Laboratory, Department of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM
Venue:
ACM SIGARCH Computer Architecture News
Year:
1989

Citing 0
Cited 2

An architecture for software-controlled data prefetching

ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Prefetch unit for vector operations on scalar computers

ACM SIGARCH Computer Architecture News

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Abstract

A variety of strategies has been proposed for fetching code and data into cache memories before it is explicitly referenced by a processor (prefetching), including both history-based and "prescient" strategies. Here, a strategy is described which treats cache blocks as components of a working set rather than merely as statistically related entities. Extension of this technique to global memory multiprocessors is discussed as a means to reduce memory contention during synchronized phase transitions.