A graph theoretic technique to speed up floorplan area optimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
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A well known approach for the floorplan area optimization problem is to first determine a list of all non-redundant implementations of the entire floorplan and then select an optimal floorplan from the list [3,5,8,9,10]. For large floorplans, this approach may fail due to insufficient memory space available to store the implementations of subfloorplans generated during the computation. An effective method to reduce memory usage is as follows: During the computation, whenever the set of non-redundant implementations of a sub-floorplan exceeds a certain predefined size, we only retain a subset of the implementations that can best approximate the original set. In this paper, we present two algorithms to optimally select implementations for rectangular and L-shaped sub-floorplans. Our algorithms are designed specifically for the floorplan optimization algorithm in [9] but they can also be applied to other algorithms such as [3,5,10] as well. The common key idea of our two algorithms is based on reducing the problem of optimally selecting a subset of implementations to a constrained shortest path problem, which we can solve optimally in polynomial time. We have incorporated the two algorithms into [9] and obtained very encouraging experimental results.