Parallel Combinator Reduction: Some Performance Bounds

  • Authors:
  • M. S. Joy;T. H. Axford

  • Affiliations:
  • -;-

  • Venue:
  • Parallel Combinator Reduction: Some Performance Bounds
  • Year:
  • 1992

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Abstract

A parallel graph reduction machine simulator is described. This performs combinator reduction and can simulate various different parallel reduction strategies. A number of functional programs are examined, and experimental results presented comparing the amount of parallelism obtainable using explicit divide-and-conquer with the maximum amount of parallelism available in the programs.