Hpsm: exploiting concurrency to achieve high performance in a single-chip microarchitecture

Exploiting parallel microprocessor microarchitectures with a compiler code generator

ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture

Forward semantic: a compiler-assisted instruction fetch method for heavily pipelined processors

MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture

Exploiting fine-grained parallelism through a combination of hardware and software techniques

ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture

ARB: A Hardware Mechanism for Dynamic Reordering of Memory References

IEEE Transactions on Computers

Control flow optimization for supercomputer scalar processing

ICS '89 Proceedings of the 3rd international conference on Supercomputing

Efficient Instruction Sequencing with Inline Target Insertion

IEEE Transactions on Computers