Area Allocation Strategies for Enhancing Yield of R-2R Ladders

  • Authors:

  • Yu Lin;Randall Geiger

  • Affiliations:

  • Department of Electrical and Computer Engineering, Iowa State University, IA 50010, USA. yulin@iastate.edu;Department of Electrical and Computer Engineering, Iowa State University, IA 50010, USA. rlgeiger@iastate.edu

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2003

Quantified Score

Hi-index 0.00

Visualization

Abstract

A new strategy for allocating area, at layout, for enhancing the soft yield of R-2R ladders is introduced. In contrast to the conventional and convenient approach of allocating equal area to each R/2R bit-slice, the new strategy allocates progressively larger areas to higher-order bits. With this strategy, the INL yield for a fixed total resistor area as determined by local random variations in the sheet resistance is optimized. Simulation results show that the new area allocation strategy provides significant improvements in INL yield compared to what is achievable with the conventional area allocation strategy.