Exact ESCT minimization for functions of up to six input variables
Integration, the VLSI Journal
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The proposed factorization methods for regular arrays of two-input cells have several important advantages over the existing logic representations and methodologies: (1) The logic representation and design implementation are consistent. (2) The stages of logic synthesis and physical design are effectively merged into a single stage. (3) The structure of the mapping solution is a regular rectangle. (4) Since the connections are mainly between neighbor cells, the wire delay is reduced comparing to other design methods. (5) Since the structure is regualr, the creation of the high-performance tools is significantly easier. (6) The methods can be applied to fine-grain FPGA design, standard cell, gate matrix layout and sub-micron technologies.