A hybrid approach for core-based system-level power modeling
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
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The very high integration rate and the increasing complexity of digital hardware architectures and embedded applications lead designers to search for new tools and methods. In order to reduce the time-to-market it becomes essential to allow designers to evaluate performances of a given application with the targetted architecture very soon in the design phase. So we have decided to build a modelling simulation environment in order to evaluate the requisite number of cycles for processing a given application with a simple model of a digital hardware architecture.Then, our main objective and the greatest part of our work is to describe this environnement with an example based on the Pine DSP and some classical digital signal processing applications : FIR, FFT butterfly, Viterbi's Butterfly.