Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications

  • Authors:
  • Jingzhao Ou;Seonil Choi;Viktor K. Prasanna

  • Affiliations:
  • -;-;-

  • Venue:
  • FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
  • Year:
  • 2003

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Abstract

Reconfigurable System-on-Chip (RSoC) devices are beingused to implement many battery operated systems,where energy efficiency is a major concern. RSoCs incorporatemany different components, such as processor core,reconfigurable logic, memory, etc. Various power managementtechniques can be applied to these components. Taskswithin an application can be mapped onto different componentsfor execution. The communication and reconfigurationcosts incurred under different mappings significantlyimpact the overall system energy dissipation. In order toachieve energy-efficient designs on RSoCs, we develop (a)a performance model to abstract a general class of RSoCarchitectures for application development, (b) a mathematicalformulation of the energy-efficient mapping problem fora class of applications, and (c) a dynamic programming algorithmthat minimizes the system energy dissipation. Weillustrate our approach by mapping two beamforming applicationsonto Xilinx Virtex-II Pro. For these two applications,our approach leads to an average 52% energy reductionover a greedy algorithm.