Novel area-efficient FPGA architectures for FIR filtering with symmetric signal extension
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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FIR filters are often used in digital signal processing.This paper presents a novel architecture for FIR filters onXilinx Virtex FPGAs. The architecture is particularly usefulfor handling the problem of signal boundaries filtering,which occurs in finite length signal processing (e.g. imageprocessing). Based on a bit parallel arithmetic, ourarchitecture is fully scalable and parameterised. It cleverlyexploits the Shift Register Logic (SRL16) component of theVirtex family. The implementation leads to considerablearea savings compared to the conventional implementation(based on a hard router) with no speed penalty. A casestudy based on the implementation of the standard low filterof the Daubechies-8 wavelet on Xilinx Virtex-E FPGAs ispresented.