Control Flow Prediction Schemes for Wide-Issue Superscalar Processors
IEEE Transactions on Parallel and Distributed Systems
Two cache lines prediction for a wide-issue micro-architecture
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
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In order to fetch a large number of instructions percycle from a sequential program, wide-issue super-scalarprocessors have to predict the outcome of multiplebranches in a cycle, and fetch instructions fromnon-contiguous portions of code.Past research has developedschemes that predict the outcome of multiplebranches by performing a single prediction.That is,instead of predicting the outcome of every conditionalbranch, a tree-like subgraph of the control flow graphof the executed program is considered as a single predictionunit, and a path is predicted through the tree,thereby allowing the superscalar fetch mechanism togo past multiple branches per cycle.In this paper, weinvestigate the potential of using different extents ofcorrelation to improve the prediction accuracy of controlflow prediction.We also investigate the potentialof increasing the tree depth to increase the fetch size.We measure the prediction accuracy of these schemesusing the SPEC '92 integer benchmarks and the MIPS-Iinstruction set.