Cyclic dependence based data reference prediction
ICS '99 Proceedings of the 13th international conference on Supercomputing
Runtime Association of Software Prefetch Control to Memory Access Instructions (Research Note)
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Design Considerations of High Performance Data Cache with Prefetching
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
A PAB-based multi-prefetcher mechanism
International Journal of Parallel Programming
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The dramatic increase in the processor-memory gapin recent years has led to the development of techniqueslike data prefetching that hide the latency of cachemisses. Two such hardware techniques are the streambuffer and the stride predictor. They have dissimilar architectures, are effective for different kinds ofmemory access patterns and require different amountsof extra memory bandwidth. We compare the performance of these two techniques and propose a schemethat unifies them1. Simulation studies on six benchmark programs confirm that the combined scheme ismore effective in reducing the average memory accesstime (AMAT) than either of the two individually.