Neural networks with chaotic recursive nodes: techniques for the design of associative memories, contrast with Hopfield architectures, and extensions for time-dependent inputs

  • Authors:
  • Emilio Del-Moral-Hernandez

  • Affiliations:
  • Department of Electronic Systems Engineering, Polytechnic School of the University of Sao Paulo, Cidade Universitaria, Av. Prof. Luciano Gualberto, Sao Paulo, Sp, CEP 05508-900, Brazil

  • Venue:
  • Neural Networks - 2003 Special issue: Advances in neural networks research — IJCNN'03
  • Year:
  • 2003

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Abstract

This paper addresses the coding and storage of information in neural architectures with bifurcating recursive nodes that exhibit chaotic dynamics. It describes architectures of coupled recursive processing elements (RPEs) used to store binary strings, discusses the choices of network parameters related to the coding of zeros and ones, and analyzes several aspects of the network operation in implementing associative memories through populations of logistic maps. Experiments for the performance evaluation of these memories are described, and results addressing the operation under digital noise (flipped bits) and analog noise added to the prompting pattern are presented and analyzed. Quantitative aspects related to the representation of binary strings through cyclic states are equated, and then related to the planning and analysis of several experiments. A simple pre-processing procedure useful in situations of prompting conditions with analog noise is proposed, and the resultant increase in recovery performance presented. The performance of the RPEs associative networks is contrasted with the performance of Hopfield associative memories, and the situations where the RPEs networks present significant superiority are identified. An extended version of the proposed architecture, which allows to address the issues of time-dependent inputs and analog inputs, is analyzed in detail. Experimental results are presented, and the role of this extended architecture in providing mechanisms for modular RPEs architectures is pointed out.