Scalable cache memory design for large-scale SMT architectures
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
Unified microprocessor core storage
Proceedings of the 4th international conference on Computing frontiers
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With shrinking feature size of silicon fabricationtechnology, architects are putting more and more logicinto a single die. While one might opt to use thesetransistors for building complex single processor basedarchitectures, recent trends indicate a shift towards on-chipmultiprocessor systems since they are simpler toimplement and can provide better performance. Animportant problem in on-chip multiprocessors is energyconsumption. In particular, on-chip cache structures canbe major energy consumers. In this work, we studyenergy behavior of different cache architectures, andpropose a new architecture, where processors share asingle, banked cache using crossbar interconnects. Ourdetailed cycle-accurate simulations show that this cachearchitecture brings energy benefits ranging from 9% to26% (over an architecture where each processor has aprivate cache).