HW/SW partitioning using discrete particle swarm
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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We present an algorithm based on dynamic programmingto perform the HW/SW partitioning and scheduling of agiven task graph for minimum latency subject to resourceconstraint. The major contribution of this paper is toconsider the edge communication delays in the dynamicprogramming solution of the problem. The algorithm has apolynomial run time complexity on trees. We alsointroduce a pruning technique to reduce the runtime of theworst-case scenario of directed acyclic graphs (DAGs).The algorithm has been implemented and the results arereported. A very fast quality heuristic is also proposed andimplemented to provide good solutions in negligible runtime.