ILP and heuristic techniques for system-level design on network processor architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Increasing link speeds have placed enormousburden on the processing requirements and theprocessors are expected to carry out a variety of tasks.Network Processors (NP) [1] [2] is the blanket namegiven to the processors, which are traded for flexibilityand performance. Network Processors are offered by anumber of vendors; to take the main burden ofprocessing requirement of network related operationsfrom the conventional processors. The NetworkProcessors cover a spectrum of design tradeoff, thatspan in between the custom ASIC and the general-purposeprocessors. IXP1200 (Intel's networkprocessor) is one among them. This paper focuses onderiving the analytical bounds on the optimum numberof threads in IXP1200 at 1Gbps wire speed.