An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs

Authors:
Radoslaw Czarnecki;Stanislaw Deniziak;Krzysztof Sapiecha
Affiliations:
-;-;-
Venue:
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Year:
2003

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Task Scheduling in a Finite-Resource, Reconfigurable Hardware/Software Codesign Environment

INFORMS Journal on Computing

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Abstract

In this work a HW/SW iterative improvement co-synthesisalgorithm, which allows for optimization ofheterogeneous system architecture with dynamicallyreconfigurable FPGAs is presented. The algorithmmaximizes speed of the system taking into considerationcost constraints.