DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
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Continual advances in the manufacturing processes of integrated circuits provide designers the ability to create more complex and denser architectures and increased functionality on a single chip. The increased usage of embedded cores necessitates a core-based test strategy in which cores are also tested separately. The IEEE P1500 proposed standard for Embedded Core Test (SECT) is a standard under development which aim is to improve the testing of core-based system chips. This paper deals with the enhancement of the Test Wrapper and Wrapper Cells to provide a structure to be able to test embedded cores for delay faults. This approach allows delay fault testing of cores by using the digital oscillation test method andthe help of the enhanced elements while staying compliant to the P1500 standard.