Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures
IEEE Transactions on Computers
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The rename map table (RMT) access and the dependence check logic(DCL) delays scale unfavorably with the dispatch width (DW) of asuperscalar processor. It is a well-known program property that theresults of most instructions are consumed within the following 4-6instruction window. This program behavior can be exploited toreduce the rename delay by reducing the number of read/write portsin the RMT to significantly below the current 3 * DW. We propose analgorithm to dynamically allocate reduced number of RMT ports toinstructions in the current dispatch window, matching dispatchresources to average needs rather than peak needs. This resultsinshorter RMT access delays as well as in lower energy in thedispatch stage. The IPC reduction due to rename map tableread/write port contention in the proposed scheme stays within2-4%. The cycle time saved can also be leverage to support widerdispatch in the same cycle time in order to offset thisdegradation.