Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
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Compiled simulation is a well known technique for improving theperformance of instruction set simulators at the cost ofcompilation time. However the compilation time overhead makes suchusage of compiler optimizations impractical especially for largeapplications. In this paper,we propose a hybrid compiled simulationapproach that is simple, generates an optimized decoder and hasalmost nocompilation overhead comparing to static compiledsimulation. Using two contemporary processor models--ARM7 andSparc--we demonstrated that our technique can reduce thecompilation time by 99% on the average, from several thousands ofseconds to only tens of seconds.