On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Complexity Effective Bypass Networks
Transactions on High-Performance Embedded Architectures and Compilers II
Single FU bypass networks for high clock rate superscalar processors
HiPC'04 Proceedings of the 11th international conference on High Performance Computing
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Modern processors rely heavily on broadcast networks to bypassinstruction results to dependent instructions in the pipeline.However, as clock rates increase, architectures get wider, andpipelines get deeper, broadcasting becomes more complex, slower,and more difficult to implement. This complexity is compounded byshrinking feature size, as the communication speed decreasesrelative to transistor switching speeds. This paper examines thefundamental needs of bypassing networks and proposes a method forclassifying these Inter-ALU Networks based on how operands arerouted from producers to consumers. We then propose and evaluate atboth the circuit and architectural level a fine grainpoint-to-point Routed Inter-ALU Network (RIAN)that delivers thesame or higher instruction throughput as a full bypass network butat higher speeds while using fewer wires.