Design Trade-Offs for User-Level I/O Architectures
IEEE Transactions on Computers
Implementation and experimental performance evaluation of a hybrid interrupt-handling scheme
Computer Communications
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As a result of technology trends towards multi-gigahertzprocessors, the I/O system is becoming a critical bottleneck formany applications. Interrupts are a major aspect of most devicedrivers. Characterizing interrupt performance and its relation toarchitectural trends is important for understanding and improvingI/O subsystem performance. Kernel instrumentation in combinationwith performance counters is able to overcome the limitations ofmicrobenchmarks when measuring interrupts. A comparative analysisof a range of IA-32 based systems reveals that interrupt handlercode exhibits only a low degree of instruction-level parallelism.Consequently, the trend towards deeper processor pipelines andsmaller caches to maximize clock frequency can be detrimental tointerrupt handling performance.