Performance evaluation of memory systems

Authors:
Mohamad R. Neilforoshan
Affiliations:
Professor, Computer Science and Information Systems, The Richard Stockton College of New Jersey, Pomona, NJ
Venue:
Journal of Computing Sciences in Colleges
Year:
2003

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Abstract

We address the issues related to the performance evaluation of the memory system in this paper. Our focus is on the problem of mismatches between block transfer time/rate among levels of the memory hierarchy. We discuss solutions, which would help reduce the effects of this problem. We provide a step-by-step approach for the evaluation of a new design. We consider both asynchronous and synchronous disk interleaving techniques and how they should be evaluated against extended-hierarchy of memory systems. We identify all the steps that are needed to make a selection among these techniques, in order to improve the performance of the computer memory system.