The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Large-scale sorting in parallel memories (extended abstract)
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
International Journal of Information Technology and Management
Multiscale visualization of dynamic software logs
EUROVIS'07 Proceedings of the 9th Joint Eurographics / IEEE VGTC conference on Visualization
A memory access model for highly-threaded many-core architectures
Future Generation Computer Systems
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The Memory Hierarchy Framework is a conceputal model together with a visual language for using the model. The model is more faithful to the structure of computers than the Von Neumann and Turing models. It addresses the issues of data movement and exposes and unifies storage mechanisms such as cache, translation lookaside buffers, main memory, and disks. The visual language presents the details of a computer's memory hierarchy in a concise drawing composed of rectangles and connecting segments. Using this framework, we have improved the performance of a matrix multiplication algorithm by more than an order of magnitude. We believe the framework gives insight into computer architecture and performance bottlenecks by making effective use of human visual abilities.