MINT: a VHDL simulation system

  • Authors:

  • Mart Altmäe

  • Affiliations:

  • Swedish Institute of Microelectronics

  • Venue:
  • EURO-DAC '90 Proceedings of the conference on European design automation
  • Year:
  • 1990

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Abstract

Several commercial VHDL simulators have been reported. Many of these however only support a subset of the language. This paper describes the development of a Multilevel INTeractive (MINT) simulator that was designed from scratch specifically for VHDL. A brief overview of the complete system is given first. Then generation of executable code for simulation purposes, and some VHDL specific features of the simulation kernel, are described.