Embedded Compact Deterministic Test for IP-Protected Cores

• Authors: Adam B. Kinsman;Jonathan I. Hewitt;Nicola Nicolici
• Venue: DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
• Year: 2003

Motivated by the dif.culty of implementing pseudo-random built-in self-test (BIST) to non-BIST-ready intellectual property (IP) cores, this paper introduces StreamBIST, a new low cost methodology for embedded deterministic test. By combining low overhead pseudo-random on-chip generation with external control for test pattern expansion, the proposed StreamBIST methodology provides maximum coverage for IP cores' compact and deterministic test sets. In addition to guaranteeing IP-protection, StreamBIST facilitates reduction in volume of test data, testing time, tester channel capacity requirements and it can seamlessly be integrated into the existing tool flows for modular system-on-a-chip (SOC) testing.