Tolerating process variations in nanophotonic on-chip networks
Proceedings of the 39th Annual International Symposium on Computer Architecture
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The exposure tool used for integrated circuit (IC) fabrication is critical to improving the packing density and transistor speed of the circuits. In addition to increasing resolution, which improves packing density and transistor speed, the exposure tool is also expected to provide tight linewidth control across the chip. Across chip linewidth variation (ACLV) has a significant influence on circuit speed. The allowed ACLV is usually assumed to be about 10% of the nominal linewidth. Therefore, just a few nanometers in linewidth variation may significantly impact IC performance. Contributions to the CD variation across chip and wafer due to lithographic sources of error are discussed in this paper. CD control afforded by future optical lithography tools is estimated using Monte Carlo aerial image simulations by making reasonable assumptions about the performance of the future tools and mask CD control. The impact of reticle enhancement technologies on ACLV is evaluated. The main sources of CD error can be identified. This approach will help define the path to improving CD control. The technique described was tested using data from the current generation of technology, and reasonable agreement between predicted and observed CD variation was obtained.