Comparison of DSP, RISC and transputer based systems for real time digital control implementation

• Authors: D. N. Ramos-Hernandez;M. O. Tokhi
• Venue: Systems Analysis Modelling Simulation - Special issue: Digital signal processing and control
• Year: 2003

An investigation into the performance evaluation of sequential and parallel computing has been carried out. Performance metrics, on the basis of maximum efficiency, have been proposed for parallel architectures. These apply to both homogeneous and heterogeneous architectures and are consistent with those of traditional architectures. These have been verified through implementation of several algorithms on uni- and multi-processor architectures. Based on the proposed concept of speedup a task allocation strategy for heterogeneous architectures has been developed. It has been demonstrated that, with such a strategy, the efficiency achieved with a heterogeneous architecture is near to its maximum value.Moreover, it has been shown that to achieve maximum efficiency a large proportion of tasks must be allocated to the faster processor of the architecture. However, due to the disparity in capabilities of the processors, communication overhead becomes a dominant factor in the implementation. Thus, to obtain a better task allocation and minimum communication overhead, high performance processors must be selected carefully.Compiler efficiency and code optimisation have been investigated showing that these affect the performance of the processors in real-time applications. The code optimisation experiments have also shown that the regularity or irregularity of the algorithm, as well as the code itself affect the performance of the processor.It has accordingly been demonstrated that different processor capabilities, communication overhead and an inappropriate task allocation can affect dramatically the performance of the application. On the other hand, a poor performance of the processor can result due to the regularity or irregularity of the application, compiler and optimisation levels of the compiler. The applications considered have varying computing requirements due to their different characteristics and different sizes. The heterogeneity present in these architectures helps to satisfy the different computing requirements of the applications.