PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design
Journal of Signal Processing Systems
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The rapidly growing number and variety of components integrated onto a single System-on-Chip is resulting in an unprecedented increase in the volume and diversity of on-chip communication traffic. However, as technology scales into the deep submicron era, chip-level communication structures are challenged by large propagation delays, signal integrity problems, and increased power consumption. Consequently, the design of the on-chip communication architecture is expected to play a significant role in determining several system-wide metrics, such as overall system performance, power consumption, and battery life. However, state-of-the-art system design methodologies, tools, and architectures are not sufficiently geared towards handling the increasing role of on-chip communication. This thesis introduces the on-chip communication architecture as a primary concern in system-level design. It addresses challenges in communication architecture design from the standpoint of methodologies and architectures for high-performance and battery-efficient System-on-Chips. The specific contributions of this thesis include: (i) system-level performance and power analysis techniques to drive the design of the communication architecture, (ii) techniques for customizing the communication architecture to characteristics of the communication traffic generated by the application, (iii) techniques for run-time adaptation of on-chip communication protocols, and (iv) a communication-based, system-level power management methodology for the design of battery-efficient systems. Experiments conducted on variety of System-on-Chip designs demonstrate that incorporation of the developed techniques into the system design process enables significant improvements in design metrics such as performance and/or battery life. In addition, the techniques described in this thesis will go a long way in facilitating research and development of design methodologies for systems based on the emerging “network-on-chip” paradigm.