A program simulator by partial interpretation

  • Authors:
  • Kazuhiro Fuchi;Hozumi Tanaka;Yuriko Manago;Toshitsugu Yuba

  • Affiliations:
  • Electrotechnical Laboratory, Japanese Government;Electrotechnical Laboratory, Japanese Government;Electrotechnical Laboratory, Japanese Government;Electrotechnical Laboratory, Japanese Government

  • Venue:
  • SOSP '69 Proceedings of the second symposium on Operating systems principles
  • Year:
  • 1969

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Abstract

In promoting the ETSS project a program simulator based on an idea of partial interpretation has been constructed, and its principle and design are described in the paper. This new approach has been introduced to provide the simulator with such features as high speed and high accuracy in simulation and simplification in implementation. The essence of the idea of partial interpretation is using direct execution of instructions by hardware and simulation of them by an interpreter in combination, wherewith the hardware interrupt mechanism intermediates the two phases of the whole simulation. An interruption takes place when executing a "privileged" instruction, which triggers the simulation of the instruction. The other type of instructions are normally rendered to direct execution by hardware. The simulation method for devices operating in parallel is also described with respect to the timing control and scheduling. A program simulator of this type provides a powerful tool for debugging "supervisor " programs and opens a new approach to system expansion.