Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Correct memory operation of cache-based multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Efficient and correct execution of parallel programs that share memory
ACM Transactions on Programming Languages and Systems (TOPLAS)
Performance evaluation of memory consistency models for shared-memory multiprocessors
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Race-free interconnection networks and multiprocessor consistency
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Distributed shared memory with versioned objects
OOPSLA '92 conference proceedings on Object-oriented programming systems, languages, and applications
The shared regions approach to software cache coherence on multiprocessors
PPOPP '93 Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming
Weak ordering—a new definition
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Concurrent Programming Concepts
ACM Computing Surveys (CSUR)
The Midway Distributed Shared Memory System
The Midway Distributed Shared Memory System
Integrating applications with cache and memory management on a shared-memory multiprocessor
CASCON '92 Proceedings of the 1992 conference of the Centre for Advanced Studies on Collaborative research - Volume 1
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The Shared Regions model introduces abstractions at the programming level that explicitly relate shared data with the synchronization primitives that guard access to that data. In this paper, we discuss consistency and event ordering in the Shared Regions model. We show that, using such a model, it is possible to relax the constraints on the ordering of memory operations beyond those possible in any of the previous memory consistency models. Additionally, we show that by taking advantage of the fact that synchronization events are labeled as readaccess or writeaccess in this model, the system can significantly improve concurrency by allowing a processor modifying some shared data to execute concurrently with processors reading that shared data. Some possible implementations exploiting the relaxed ordering constraints and increased concurrency are also discussed.