Sizing Consideration for Leakage Control Transistor

  • Authors:
  • F. Farbiz;M. Farazian;M. Emadi;K. Sadeghi

  • Affiliations:
  • -;-;-;-

  • Venue:
  • VLSID '04 Proceedings of the 17th International Conference on VLSI Design
  • Year:
  • 2004

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Abstract

In this paper, we report the use of the GeneticAlgorithm (GA) to determine the optimum size of theleakage control transistor for low power applications. Inthe optimization, the energy-delay product is minimized.The transistor is modeled by a neural network to increasethe speed and the accuracy of the calculations.