HiPC'05 Proceedings of the 12th international conference on High Performance Computing
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A key component of the Data-Intensive Architecture(DIVA) is the Processing-In-Memory (PIM) RoutingComponent (PiRC) that is responsible for efficientcommunication between PIM chips. This paperpresents the design of a low area, delay and powerrouter for DIVA. A 58.5% saving in area and 86%reduction in load on the clock as compared to anearlier PIM router design makes the presented designideal for use in the second version of DIVA, with lowarea being a critical design requirement for DIVA.This paper also gives a comparison of the presenteddesign with an earlier PIM router design in terms ofdelay and power to justify the new design choice.