Robust estimation of parametric yield under limited descriptions of uncertainty
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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CMOS technology has witnessed aggressivescaling over the last couple of decades. This hasresulted in better performance, higherintegration density and increased on-chipfunctionality. The threshold voltage has beenaggressively scaled down, oxides have beendrastically thinned and the MOS transistorchannels have been suitable engineered to meetthe high performance criteria. However, allthese have resulted in an increase in transistorleakage and have posed serious bottlenecks tofurther 'scale' these super-scaled devices. Thispaper explores the various dominant leakagemechanisms in scaled devices and examines theirtrends with scaling. Leakage estimation incircuits has also been presented.