A Solution for the N-bit Parity Problem Using a Single Translated Multiplicative Neuron

Authors:
Eduardo Masato Iyoda;Hajime Nobuhara;Kaoru Hirota
Affiliations:
Department of Computational Intelligence and Systems Science, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8 ...;Department of Computational Intelligence and Systems Science, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8 ...;Department of Computational Intelligence and Systems Science, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8 ...
Venue:
Neural Processing Letters
Year:
2003

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Abstract

A solution to the N-bit parity problem employing a single multiplicative neuron model, called translated multiplicative neuron (πt-neuron), is proposed. The πt-neuron presents the following advantages: (a) ∀N≥1, only 1 πt-neuron is necessary, with a threshold activation function and parameters defined within a specific interval; (b) no learning procedures are required; and (c) the computational cost is the same as the one associated with a simple McCulloch-Pitts neuron. Therefore, the πt-neuron solution to the N-bit parity problem has the lowest computational cost among the neural solutions presented to date.