Digital emulator and observer of multicell converter

Authors:
R. Ruelland;G. Gateau;T. Meynard;J. C. Hapiot
Affiliations:
LEEI-Laboratoire d'Electrotechnique et d'Electronique Industrielle, Unité Mixte de Recherche, INPT-ENSEEIHT/CNRS, B.P. 7122-2, rue Camichel 31071, Toulouse Cedex 7, France;LEEI-Laboratoire d'Electrotechnique et d'Electronique Industrielle, Unité Mixte de Recherche, INPT-ENSEEIHT/CNRS, B.P. 7122-2, rue Camichel 31071, Toulouse Cedex 7, France;LEEI-Laboratoire d'Electrotechnique et d'Electronique Industrielle, Unité Mixte de Recherche, INPT-ENSEEIHT/CNRS, B.P. 7122-2, rue Camichel 31071, Toulouse Cedex 7, France;LEEI-Laboratoire d'Electrotechnique et d'Electronique Industrielle, Unité Mixte de Recherche, INPT-ENSEEIHT/CNRS, B.P. 7122-2, rue Camichel 31071, Toulouse Cedex 7, France
Venue:
Mathematics and Computers in Simulation - Special issue: Modelling and simulation of electrical machines, converters and systems
Year:
2003

Citing 2
Cited 1

Software timing analysis using HW/SW cosimulation and instruction set simulator

Proceedings of the 6th international workshop on Hardware/software codesign
Hardware, Software and Mechanical Cosimulation for Automotive Applications

RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping

Modeling and stability analysis of cascade buck converters with N power stages

Mathematics and Computers in Simulation

Quantified Score

Hi-index	0.00

Visualization

Abstract

This article presents the design of a digital real-time emulator dedicated to the simulation of four-level multicell converter. The design has been made using a new tool: the co-simulation. Co-simulation results are presented in this paper and an experimental setup has been realised on a FPGA1 in order to validate this new tool. In the final part, we present the test of an observation loop using this emulator.