Analysis and optimization of thermal issues in high-performance VLSI
Proceedings of the 2001 international symposium on Physical design
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Joule heating in interconnects raises the temperature of the metals above that of the substrate, which impacts both performance and reliability of Integrated Circuits. The resistivity of the metal depends on temperature, surface scattering and the thickness of the resistive diffusion barrier. The effective thermal conductivity of inter-layer dielectrics (ILD) depends on the vias. In this work, we account for all these dependencies to determine the temperature profile in the metal lines; the resulting performance is also studied. Two configurations are considered, both of which incorporate low-k materials in the backend: one in which both the ILD and inter-metal dielectric (IMD) are replaced by low-k material (homogeneous), and the other in which only the IMD is replaced by low-k, and SiO2 is used as the ILD material (non-homogenous). We find that the temperature excursion at the top metal level (relative to the substrate) increases approximately by a factor of 10 in the first case versus 3 for the second by the year 2016. Using the above Joule heating model, coupled with electromigration model, we compare the maximum allowed current density dictated by electromigration constraints for the two low-k technology options.