A hardware extension of the RISC microprocessor for Attribute Grammar evaluation

  • Authors:

  • Ioannis Panagopoulos;Christos Pavlatos;George Papakonstantinou

  • Affiliations:

  • National Technical University of Athens, Iroon Polytexneiou, Zografou, Athens;National Technical University of Athens, Iroon Polytexneiou, Zografou, Athens;National Technical University of Athens, Iroon Polytexneiou, Zografou, Athens

  • Venue:
  • Proceedings of the 2004 ACM symposium on Applied computing
  • Year:
  • 2004

Quantified Score

Hi-index 0.00

Visualization

Abstract

Conventional implementations of Attribute Grammar (AG) evaluators in embedded systems today, are solely of software nature. A compiler transforms the parser's specification along with the declarative attribute evaluation rules into a behaviorally equivalent procedural program to be executed on the microprocessor. This approach affects the final system's performance as well as the complexity of the final implementation. Efforts in presenting hardware implementations of AG evaluators, although efficient enough in terms of performance, are usually fully implemented in hardware and as a consequence restricted to a single application. We exploit HW/SW codesign methods in the effort of presenting a hardware implementation of AG evaluators that is both reprogrammable and increases the desired system's performance. We achieve that by extending a conventional RISC microprocessor by combining it with a programmable implementation of a hardware parser to propose a fully programmable AG evaluator that supports the execution of hybrid combinations of declarative-procedural code. The hardware parser increases design efficiency of tree derivations while the RISC microprocessor handles the attribute evaluation computations. As a result, performance is increased while design flexibility required in embedded system applications is preserved.